The present invention relates to microelectronic devices and, and more specifically, to controlling warpage of the laminate on which other microelectronic devices may reside.
Once formation of semiconductor devices and interconnects on a semiconductor wafer is completed, the semiconductor wafer is diced into semiconductor chips, or “dies.” Functional semiconductor chips are then packaged to facilitate mounting to a larger device.
The packaging generally provides mechanical protection and electrical connections to an external element. One typical packaging technology is Controlled Collapse Chip Connection (C4) packaging, which employs C4 balls each of which contacts a C4 pad on the semiconductor chip and another C4 pad on a packaging substrate. The packaging substrate may then be assembled on a larger circuit board. The combined chip and laminate may be referred to as a module in some cases. Of course, a module may include other elements such as a lid.
Mounting electrical components such as discrete resistors, discrete capacitors, transistors, digital circuits, etc. on laminate is well known. It is common for such laminate to contain many layers. Typically, most of the components are mounted on the surface. Some of the conductors used to interconnect the components may also be printed on the surface. The inner layers are primarily used to interconnect the components through other conductors printed on these inner layers and conductive vias passing through the outer and inner layers. For complex circuits, the surface area must be carefully allocated to fit the many requisite components. Also, in the case of capacitor components, it is desirable to position some of the capacitors near other, associated components to minimize path length and thereby minimize parasitic inductance.
As will be understood, greater the number of interconnects in a particular area, the more likely it is that differences in a coefficient of thermal expansion (CTE) between the interconnect (e.g., wires) and the surrounding laminate material may result in deformation of the laminate in such a region. The deformation can lead to buckling or other deformation of laminate. This may, in turn, cause connections on the surface to break. One such possible break may occur between the capacitors and the die. Of course, buckling or other deformation could cause other defects or malfunctions to occur as well.
Further, in operation, the die may include some areas that run hotter than others. This can, again, lead to stresses experience by connections (e.g., the C4) between the die and the laminate. Such stresses can, in severe cases, lead to a broken connection which can reduce the effectiveness of a particular die.